functional diagrams for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim?s website at www.maxim integrated .com. general description the ds1990a serial number i button is a rugged data carrier that serves as an electronic registration numberfor automatic identification. data is transferred serially through the 1-wire protocol, which requires only a sin- gle data lead and a ground return. every ds1990a isfactory lasered with a guaranteed unique 64-bit regis- tration number that allows for absolute traceability. the durable stainless-steel i button package is highly resis- tant to environmental hazards such as dirt, moisture,and shock. its compact coin-shaped profile is self- aligning with mating receptacles, allowing the ds1990a to be used easily by human operators. accessories enable the ds1990a i button to be mounted on almost any object, including containers, pallets, and bags. applications access controlwork-in-progress tracking tool management inventory control features ? can be read in less than 5ms ? operating range: 2.8v to 6.0v, -40? to +85? common i button features ? unique factory-lasered 64-bit registrationnumber ensures error-free device selection and absolute traceability because no two parts are alike ? built-in multidrop controller for 1-wire net ? digital identification by momentary contact ? data can be accessed while affixed to object ? economically communicates to bus master witha single digital signal at 16.3kbps ? button shape is self-aligning with cup-shapedprobes ? durable stainless-steel case engraved withregistration number withstands harsh environments ? easily affixed with self-stick adhesive backing,latched by its flange, or locked with a ring pressed onto its rim serial number i button pin configurations ordering information rev: 10/08 part temp range pin-package ds1990a-f5+ -40 c to +85 c f5 i button ds1990a-f3+ -40 c to +85 c f3 i button examples of accessories part accessory ds9096p self-stick adhesive pad ds9101 multipurpose clip ds9093ra mounting lock ring ds9093a snap-in fob ds9092 i button probe 16.25mm 5.89mm 0.51mm 3.10mm 0.51mm 17.35mm branding f5 size gnd gnd io io f3 size 89 01 000000fbc52b 1-wire i b u t t o n . c o m y y w w z z z d s 1 9 9 0 a + f 5 i button and 1-wire are registered trademarks of maxim integrated products, inc. + denotes a lead(pb)-free/rohs-compliant package. ds1990a ordering information downloaded from: http:/// available
serial number i button absolute maximum ratingselectrical characteristics (t a = -40? to +85?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 1: all voltages are referenced to ground. note 2: external pullup voltage. see figure 4. note 3: system requirement. note 4: full r pup range is guaranteed by design and simulation and not production tested. production testing performed at a fixed r pup value. maximum allowable pullup resistance is a function of the number of 1-wire devices in the system and 1- wire recovery times. the specified value here applies to systems with only one device and with the minimum 1-wire recov-ery times. for more heavily loaded systems, an active pullup such as that found in the ds2480b may be required. note 5: capacitance on the io pin could be 800pf when power is first applied. if a 5k resistor is used to pull up the io line to v pup , 5? after power has been applied the parasite capacitance will not affect normal communications. note 6: guaranteed by design, simulation only. not production tested. note 7: input load is to ground. io voltage range to gnd .....................................-0.5v to +6.0v io sink current....................................................................20ma junction temperature ......................................................+125? storage temperature range .............................-55? to +125? parameter symbol conditions min typ max units io pin: general data 1-wire pullup voltage v pup (notes 1, 2) 2.8 6.0 v 1-wire pullup resistance r pup (notes 3, 4) 0.6 5 k input capacitance c io (notes 5, 6) 100 800 pf input load current i l (note 7) 0.25 a input low voltage v il (notes 1, 3, 8) 0.3 v input high voltage v ih (notes 1, 9) 2.2 v output low voltage at 4ma v ol (note 1) 0.4 v operating charge q op (notes 6, 10) 30 nc recovery time t rec (note 3) 1 s time slot duration t slot (note 3) 61 s io pin: 1-wie reset, presence-detect cycle reset low time t rstl (notes 3, 11) 480 s reset high time t rsth (notes 3, 12) 480 s presence-detect high time t pdh 15 60 s presence-detect low time t pdl (note 13) 60 240 s presence-detect sample time t msp (note 3) 60 75 s io pin: 1-wie write write-zero low time t w0l (notes 3, 14) 60 120 s write-one low time t w1l (notes 3, 14) 1 15 s io pin: 1-wie read read low time t rl (notes 3, 15) 1 15 - s read sample time t msr (notes 3, 15) t rl + 15 s ds1990a 2 maxim integrated downloaded from: http:///
serial number i button note 8: the voltage on io must be less than or equal to v ilmax whenever the master drives the line low. note 9: v ih is a function of the internal supply voltage. note 10: 30nc per 72 time slots at 5.0v pullup voltage with a 5k pullup resistor and t slot 120?. note 11: the reset low time (t rstl ) should be restricted to a maximum of 960? to allow interrupt signaling. a longer duration could mask or conceal interrupt pulses if this device is used in parallel with a ds1994. note 12: an additional reset or communication sequence cannot begin until the reset high time has expired. note 13: presence pulse is guaranteed only after a preceding reset pulse (t rstl ). note 14: in figure 7 represents the time required for the pullup circuitry to pull the voltage on io up from v il to v ih . the actual maximum duration for the master to pull the line low is t w1lmax + t f - and t w0lmax + t f - , respectively. note 15: in figure 7 represents the time required for the pullup circuitry to pull the voltage on io up from v il to the input-high threshold of the bus master. the actual maximum duration for the master to pull the line low is t rlmax + t f . i button can physical specification size see the package information section. weight (ds1990a) ca. 2.5 grams detailed description the block diagram in figure 1 shows the major functionblocks of the device. the ds1990a takes the energy it needs to operate from the io line, as indicated by the parasite power block. the rom function control unitincludes the 1-wire interface and the logic to implement the rom function commands, which access 64 bits of lasered rom. ds1990a parasite power rom function control io 64-bit lasered rom figure 1. block diagram ds1990a maxim integrated 3 downloaded from: http:///
64-bit lasered rom each ds1990a contains a unique rom code that is 64bits long. the first 8 bits are a 1-wire family code. the next 48 bits are a unique serial number. the last 8 bits are a crc of the first 56 bits. see figure 2 for details. the 1-wire crc is generated using a polynomial gen- erator consisting of a shift register and xor gates as shown in figure 3. the polynomial is x 8 + x 5 + x 4 + 1. additional information about the 1-wire cyclicredundancy check (crc) is available in application note 27: understanding and using cyclic redundancy checks with maxim i button products. the shift register bits are initialized to 0. then startingwith the least significant bit of the family code, one bit at a time is shifted in. after the 8th bit of the family code has been entered, the serial number is entered. after the 48th bit of the serial number has been entered, the shift register contains the crc value. shifting in the 8 bits of crc returns the shift register to all 0s. 1-wire bus system the 1-wire bus is a system that has a single bus masterand one or more slaves. in all instances, the ds1990a is a slave device. the bus master is typically a micro- controller or pc. for small configurations, the 1-wire communication signals can be generated under soft- ware control using a single port pin. alternatively, the ds2480b 1-wire line driver chip or serial-port adapters based on this chip (ds9097u series) can be used. this simplifies the hardware design and frees the micro- processor from responding in real time. the discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-wire signaling (signal types and timing). the 1-wire protocol defines bus transactions in terms of the bus state during specific time slots that are initiated on the falling edge of sync pulses from the bus master. for a more detailed protocol description, refer to chapter 4 of the book of i button standards . serial number i button msb 8-bit crc code 48-bit serial number msb msb lsb lsblsb 8-bit family code (01h) msb lsb figure 2. 64-bit lasered rom 1st stage 2nd stage 3rd stage 4th stage 7th stage 8th stage 6th stage 5th stage x 0 x 1 x 2 x 3 x 4 polynomial = x 8 + x 5 + x 4 + 1 input data x 5 x 6 x 7 x 8 figure 3. 1-wire crc generator ds1990a 4 maxim integrated downloaded from: http:///
hardware configuration the 1-wire bus has only a single line by definition; it isimportant that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1-wire bus must have open-drain or three-state outputs. the 1-wire port of the ds1990a is open drain with an internal circuit equivalent to that shown in figure 4. a multidrop bus consists of a 1-wire bus with multiple slaves attached. at standard speed, the 1-wire bus has a maximum data rate of 16.3kbps. the value of the pullup resistor primarily depends on the network size and load conditions. for most applica- tions, the optimal value of the pullup resistor is approxi- mately 2.2k . the idle state for the 1-wire bus is high. if for any reason a transaction needs to be suspended,the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 120?, one or more devices on the busmay be reset. transaction sequence the protocol for accessing the ds1990a through the1-wire port is as follows: initialization rom function command initialization all transactions on the 1-wire bus begin with an initial-ization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that the ds1990a is on the bus and is ready to operate. for more details, see the 1-wire signaling section. serial number i button rx r pup v pup simple bus master ds2480b bus master open-drain port pin 100 mosfet tx rxtx data ds1990a 1-wire port rx = receive tx = transmit v dd polrxd serial in serial out txd v pp gnd n.c. 1-w to 1-wire data +5v host cpu serial port ds2480b figure 4. hardware configuration ds1990a maxim integrated 5 downloaded from: http:///
1-wire rom function commands once the bus master has detected a presence, it canissue one of the rom function commands the ds1990a supports. all rom function commands are 8 bits long. a list of these commands follows. (see figure 5 for a flowchart.) read rom [33h] this command allows the bus master to read theds1990a? 8-bit family code, unique 48-bit serial num- ber, and 8-bit crc. this command can only be used if there is a single slave device on the bus. if more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the same time (open drain pro- duces a wired-and result). the resultant family code and 48-bit serial number results in a mismatch of the crc. search rom [f0h] when a system is initially brought up, the bus mastermight not know the number of devices on the 1-wire bus or their registration numbers. by taking advantage of the wired-and property of the bus, the master can use a process of elimination to identify the registration numbers of all slave devices. for each bit of the regis- tration number, starting with the least significant bit, the bus master issues a triplet of time slots. on the first slot, each slave device participating in the search outputs the true value of its registration number bit. on the sec- ond slot, each slave device participating in the search outputs the complemented value of its registration num- ber bit. on the third slot, the master writes the true value of the bit to be selected. all slave devices that do not match the bit written by the master stop participat- ing in the search. if both of the read bits are zero, the master knows that slave devices exist with both states of the bit. by choosing which state to write, the bus master branches in the rom code tree. after one com- plete pass, the bus master knows the registration num- ber of a single device. additional passes identify the registration numbers of the remaining devices. refer to application note 187: 1-wire search algorithm for a detailed discussion, including an example. match rom [55h]/skip rom [cch] the minimum set of 1-wire rom function commandsincludes a match rom and a skip rom command. because the ds1990a contains only the 64-bit rom without any additional data fields, match rom and skip rom are not applicable. the ds1990a remains silent (inactive) upon receiving a rom function command that it does not support. this allows the ds1990a to coexist on a multidrop bus with other 1-wire devices that do respond to match rom or skip rom. serial number i button ds1990a tx presence pulse bus master tx reset pulse bus master tx rom function command ds1990a tx crc byte ds1990a tx family code (1 byte) ds1990a tx serial number (6 bytes) y 33h read rom command? n bit 0 match? n n n f0h search rom command? n y y ds1990a tx bit 0 ds1990a tx bit 0 master tx bit 0 y bit 1 match? bit 63 match? ds1990a tx bit 1 ds1990a tx bit 1 master tx bit 1 ds1990a tx bit 63 ds1990a tx bit 63 master tx bit 63 y figure 5. rom functions flowchart ds1990a 6 maxim integrated downloaded from: http:///
1-wire signaling the ds1990a requires strict protocols to ensure dataintegrity. the protocol consists of four types of signaling on one line: reset sequence with reset pulse and pres- ence pulse, write-zero, write-one, and read-data. except for the presence pulse, the bus master initiates all these signals. to get from idle to active, the voltage on the 1-wire line needs to fall from v pup to below v ilmax . to get from active to idle, the voltage needs to rise from v ilmax to above v ihmin . the time it takes for the voltage to make this rise, referenced as in figure 6, depends on the value of the pullup resistor (r pup ) and capacitance of the 1-wire network attached.the initialization sequence required to begin any com- munication with the ds1990a is shown in figure 6. a reset pulse followed by a presence pulse indicates that the ds1990a is ready to receive a rom function com- mand. if the bus master uses slew-rate control on the falling edge, it must pull down the line for t rstl + t f to compensate for the edge.after the bus master has released the line, it goes into receive mode (rx). now the 1-wire bus is pulled to v pup through the pullup resistor or, in the case of a ds2480b driver, by active circuitry. when the v ihmin is crossed, the ds1990a waits for t pdh and then transmits a presence pulse by pulling the line low for t pdl . to detect a presence pulse, the master must test the logi-cal state of the 1-wire line at t msp . read/write time slots data communication with the ds1990a takes place intime slots that carry a single bit each. write time slots transport data from bus master to slave. read time slots transfer data from slave to master. the definitions of the write and read time slots are illustrated in figure 7. all communication begins with the master pulling the data line low. as the voltage on the 1-wire line falls below v ilmax , the ds1990a starts its internal timing generator that determines when the data line is sam-pled during a write time slot and how long data is valid during a read time slot. master-to-slave for a write-one time slot, the voltage on the data line must have risen above v ihmin after the write-one low time t w1lmax is expired. for a write-zero time slot, the voltage on the data line must stay below v ilmax until the write-zero low time t w0lmin is expired. for most reli- able communication, the voltage on the data lineshould not exceed v ilmax during the entire t w0l win- dow. after the voltage has risen above v ihmin , the ds1990a needs a recovery time t rec before it is ready for the next time slot. serial number i button resistor master ds1990a t rstl t pdl t rsth t pdh master tx "reset pulse" master rx "presence pulse" v pup v ihmin v ilmax 0v t f t rec t msp figure 6. initialization procedure: reset and presence pulses ds1990a maxim integrated 7 downloaded from: http:///
serial number i button resistor master resistor master resistor master ds1990a v pup v ihmaster v ihmin v ilmax 0v t f v pup v ihmaster v ihmin v ilmax 0v t f v pup v ihmaster v ihmin v ilmax 0v t f t slot t w1l t rec t slot t slot t w0l t rec master sampling window t rl t msr write-one time slotwrite-zero time slot read-data time slot figure 7. read/write timing diagram ds1990a 8 maxim integrated downloaded from: http:///
slave-to-master a read-data time slot begins like a write-one time slot. the voltage on the data line must remain below v ilmax until the read low time t rl is expired. during the t rl window, when responding with a 0, the ds1990a startspulling the data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. when responding with a 1, the ds1990a does not hold the data line low at all, and the voltage starts rising as soon as t rl is over. the sum of t rl + (rise time) on one side and the inter- nal timing generator of the ds1990a on the other sidedefine the master sampling window (t msrmin to t msrmax ) in which the master must perform a read from the data line. for most reliable communication, t rl should be as short as permissible and the master shouldread close to but no later than t msrmax . after reading from the data line, the master must wait until t slot is expired. this guarantees sufficient recovery time t rec for the ds1990a to get ready for the next time slot. serial number i button package type package code document no. f3 i button ib#3nb 21-0252 f5 i button ib#5nb 21-0266 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . ds1990a maxim integrated 9 downloaded from: http:///
serial number i button revision history revision date description pages changed 033005 redid the formatting based on newer template style. also deleted the 0f read rom command and added a note about presence pulse criteria. 1C8 created newer template-style data s heet. all updated ordering information with lead-free part numbers. 1 deleted meets ul 913 (4th edit); intrinsicall safe apparatus: approved under entit concept for use in class i, division i, group a, b, c, and d from the common i button features and i button can phsical specification sections. 1, 3 updated electrical characteristics table: deleted output high voltage parameter. moved 1-wire pullup voltage parameter from table header to table body. changed v ilmax from 0.8v to 0.3v. added note 14 to the t w0l specification. changed t w1lmax from 15s C to 15s. 2 10/08 added the epsilon timing to the write-zero time slot in figure 7. 8 ds1990a downloaded from: http:/// 0 d [ l p , q w h j u d w h g 5 l r 5 r e o h v 6 d q - r v h & $ 8 6 $ maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. ? maxim integrated the maxim logo and maxim integrated are trademarks of maxim integrated products, inc.
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